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https://www.nxp.com/docs/en/data-sheet/LPC2468.pdf писал(а):NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory.
DBGEN 9[1][8] F4[1][8] I DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO 2[1][9] D3[1][9] O TDO — Test Data Out for JTAG interface.
TDI 4[1][8] C2[1][8] I TDI — Test Data In for JTAG interface.
TMS 6[1][8] E3[1][8] I TMS — Test Mode Select for JTAG interface.
TRST 8[1][8] D1[1][8] I TRST — Test Reset for JTAG interface.
TCK 10[1][9] E2[1][9] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK 206[1][8] C3[1][8] I/O RTCK — JTAG interface control signal
7.2 On-chip flash programming memory.
The LPC2468 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished inseveral ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades. The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz.
7.26.3 Code security (Code Read Protection - CRP)
This feature of the LPC2468 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10]/EINT0 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
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