Сб ноя 24, 2012 15:39:16
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
ENTITY ron IS
PORT
(
clk : IN std_logic;
INTA : IN std_logic;
DATA_IN : IN std_logic_vector (11 DOWNTO 0);
ADR_REG1 : IN std_logic_vector (3 DOWNTO 0);
ADR_REG2 : IN std_logic_vector (3 DOWNTO 0);
WE : IN std_logic;
DATA_OUT1 : OUT std_logic_vector (11 DOWNTO 0);
DATA_OUT2 : OUT std_logic_vector (11 DOWNTO 0)
);
END ron;
ARCHITECTURE arh OF ron IS
type registr is array (0 to 15) of std_logic_vector(11 downto 0);
signal reg : registr;
signal reg_buff : registr;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (WE = '1') THEN
reg(to_integer(unsigned(ADR_REG2)))<=DATA_IN;
ELSE
DATA_OUT1<=reg(to_integer(unsigned(ADR_REG1)));
DATA_OUT2<=reg(to_integer(unsigned(ADR_REG2)));
END IF;
END IF;
if(rising_edge(INTA)) then
reg_buff<=reg;
end if;
if(FALLING_EDGE(INTA)) then
reg<=reg_buff;
end if;
END PROCESS;
END arh;
Сб ноя 24, 2012 16:07:43
PROCESS(clk)
BEGIN
IF (clk'event AND clk = '1') THEN
if(rising_edge(INTA)) then
Сб ноя 24, 2012 16:41:56
Сб ноя 24, 2012 19:14:25