Вс фев 26, 2023 16:18:07
module sr_latch(input s, r, output p, q);
assign q = ~(r | p);
assign p = ~(s | q);
endmodule
module top(input clk,
input [1:0] key,
output [7:0] ledr);
assign ledr[7:2] = 6'b0;
sr_latch sr_latch
(
.s(~key[0]),
.r(~key[1]),
.q(ledr[0]),
.p(ledr[1])
);
endmodule
module top(input clk,
input [1:0] key,
output [7:0] ledr);
assign ledr[7:2] = 6'b0;
sr_latch sr_latch
(
.s(key[0]),
.r(key[1]),
.q(ledr[0]),
.p(ledr[1])
);
endmodule
Вс фев 26, 2023 16:31:33
Вс фев 26, 2023 16:35:11
Вс фев 26, 2023 16:37:27
Вс фев 26, 2023 17:27:35