Чт мар 10, 2016 13:56:45
module LED
(
input CLK,
output [7:0] LED_Out,
input RST
);
reg [8:0] count = 8'b1;
reg [24:0] ctr = 24'b0;
always @(posedge CLK )
begin
if (RST == 0)
begin
ctr = 24'b0;
end
ctr = ctr + 1;
if(ctr == 0)
begin
count[8:0] <= {count[0], count[8:1]};
end
end
assign LED_Out = count [7:0];
endmodule
Чт мар 10, 2016 18:01:43