Чт мар 06, 2014 22:52:05
assign sr_out = sr[7:0];
assign sr_out1 = sr[15:8];
assign sr_out2 = sr[23:16];
assign sr_out3 = sr[31:24];
module counter (
shift,
clk,
sr_in,
sr_out,
sr_out1,
sr_out2,
sr_out3,
sr_out4
);
input shift,clk;
input wire [7:0]sr_in;
output [7:0]sr_out,sr_out1,sr_out2,sr_out3,sr_out4;
reg [31:0]sr;
always @ (posedge clk)
if (shift ==1 )
sr <= { sr[23:0],sr_in };
parameter SIZE = 4;
genvar i;
generate
for (i=1; i <= SIZE; i=i+1)
begin: bit
assign sr_out[i] = sr[i*8-1:(i-1)*8];
end
endgenerate
Пт мар 07, 2014 07:58:45
leonem писал(а):Хочу заменить
- Код:
assign sr_out = sr[7:0];
assign sr_out1 = sr[15:8];
assign sr_out2 = sr[23:16];
assign sr_out3 = sr[31:24];
на assign sr_out[i] = sr[i*8-1:(i-1)*8]; но к сожалению это не получается не понимаю почему
output [7:0]sr_out,sr_out1,sr_out2,sr_out3,sr_out4;
output [3:0][7:0]sr_out;
Пт мар 07, 2014 17:00:19
Ср мар 19, 2014 22:03:34
module counter (
shift,
clk,
sr_in,
sr_out,
sr_out1,
sr_out2,
sr_out3,
sr_out4
);
input shift,clk;
input wire [7:0]sr_in;
output [7:0]sr_out,sr_out1,sr_out2,sr_out3,sr_out4;
reg [3:0]counte=4'b0;
reg [7:0] sr [3:0];
integer n;
reg [7:0]v =8'h57;
reg [7:0]a;
wire c;
always @(posedge clk)
if (shift ==1)
begin
if(counte==4'd4) counte <= 4'b0;
else counte <= counte + 1'd1;
for (n = 0; n<4; n = n+1)
begin
sr[0] <= sr_in;
sr[n] <=sr[n-1];
$display("%d",n,sr[n]);
end
end
assign c = counte == 4'd4;
assign sr_out = sr[0];
assign sr_out1 = sr[1];
assign sr_out2 = sr[2];
assign sr_out3 = sr[3];
always @ (posedge clk)
if(c==1)
begin
a <= v+ sr[2];
$display("%d",n,a);
end
initial
$monitor($stime,, shift,, clk,,,sr_out,sr_out1,a, sr_in );
endmodule
Вс мар 23, 2014 16:07:39