Вт дек 27, 2022 11:37:38
#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();} if(StartUpCounter == 0xffffff) return 0;}while(0)
int StartHSE(){ // fVCO can be from 192 to 432MHz
__IO uint32_t StartUpCounter = 0;
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSEON; // disable PLL to reconfigure, enable HSE
WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
/* Enable high performance mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
// HCLK = SYSCLK, PCLK1 = HCLK/4, PCLK2 = HCLK/2
RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)
) | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
RCC->CR |= RCC_CR_PLLON; // Enable PLL
// Wait till PLL is ready
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
// Select PLL as system clock source
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// Wait till PLL is used as system clock source
WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
return 1;
}
Вт дек 27, 2022 13:51:25
Вт дек 27, 2022 13:58:08
Вт дек 27, 2022 14:16:22
Вт дек 27, 2022 14:24:55
Вт дек 27, 2022 15:09:22
Line number 106 out of range; blink.c has 105 lines.
Вт дек 27, 2022 15:56:18
Вт дек 27, 2022 16:18:15
void WEAK __attribute__ ((noreturn)) reset_handler(void){
extern char _sdata; // .data section start
extern char _edata; // .data section end
extern char _sbss; // .bss section start
extern char _ebss; // .bss section end
extern char _ldata; // .data load address
char *dst = &_sdata;
char *src = &_ldata;
SCB->VTOR = FLASH_BASE;
/* FPU settings ----------*/
#if (__FPU_PRESENT == 1)
SCB->CPACR = 0x0f << 20 ; /* set CP10 and CP11 Full Access */
nop();
__DSB();
__ISB();
#else
#pragma message("FPU not present")
#endif
while ( dst < &_edata ) { *dst++ = *src++; }
for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; }
main();
for(;;) {}
}
Вт дек 27, 2022 16:50:02
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
Вт дек 27, 2022 17:06:41
Кстати, а где ты так искусно FPU научился включать?
ENTRY(reset_handler)
SECTIONS {
.vector_table 0x08000000 :
{
_sisrvectors = .;
KEEP(*(.vector_table))
/* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
_eisrvectors = .;
} >rom
.text :
{
. = ALIGN(4);
_stext = .;
*(.text*)
*(.rodata*)
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .;
} >rom
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >rom
.ARM : {
*(.ARM.exidx*)
} >rom
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data*)
. = ALIGN(4);
_edata = .;
} >ram AT >rom
.myvars :
{
. = ALIGN(2048);
__varsstart = ABSOLUTE(.);
KEEP(*(.myvars))
} > rom
_ldata = LOADADDR(.data);
.ccmram :
{
. = ALIGN(4);
_sccmram = .;
*(.ccmram)
*(.ccmram*)
. = ALIGN(4);
_eccmram = .;
} >ccmram AT> rom
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >ram
}
PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ccmram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
}
INCLUDE stm32f4.ld
Вт дек 27, 2022 17:15:56
Вт дек 27, 2022 17:33:45
Вт дек 27, 2022 17:37:56
Вт дек 27, 2022 17:40:33
Ср дек 28, 2022 15:05:11
PWR->CR |= PWR_CR_VOS;
Ср дек 28, 2022 16:16:26
Чт дек 29, 2022 09:32:40
PWR->CR |= PWR_CR_VOS;
Пт дек 30, 2022 08:59:49
Пт дек 30, 2022 10:04:34
Пт дек 30, 2022 10:31:13
Стесьняюсь спросить, а про "read protection Level 2" ты что-нибудь слышал/читал?