Вс фев 13, 2022 22:07:30
Вс фев 13, 2022 22:27:24
TRUE_INLINE int StartHSE(){ // system bus 72MHz from PLL
__IO uint32_t StartUpCounter = 0;
#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}; if(x) return 0;}while(0)
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSEON; // disable PLL to reconfigure, enable HSE
WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
// Enable Prefetch Buffer. Flash 4 wait states for 48..72MHz
FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) |
FLASH_ACR_LATENCY_2 | FLASH_ACR_PRFTBE;
// HCLK = SYSCLK (AHB prescaler = 1), PCLK1 = HCLK (APB1 prescaler = 1), PCLK2 = HCLK (APB2 prescaler = 1)
// PLLCLK = HSE * 9 = 72MHz
RCC->CFGR = RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL9;
RCC->CR |= RCC_CR_PLLON; // Enable PLL
// Wait till PLL is ready
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
// Select PLL as system clock source
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// Wait till PLL is used as system clock source
WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1);
#undef WAITWHILE
return 1;
}
Вс фев 13, 2022 22:37:17
FLASH->ACR = FLASH_ACR_PRFTBE | _VAL2FLD(FLASH_ACR_LATENCY,2);
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_HSION | RCC_CR_HSEON;
while(!(RCC->CR & RCC_CR_HSERDY));
RCC->CFGR = RCC_CFGR_MCO_NOCLOCK
| RCC_CFGR_I2SSRC_SYSCLK
| RCC_CFGR_USBPRE_DIV1_5
| RCC_CFGR_PLLMUL9
| RCC_CFGR_PLLSRC_HSE_PREDIV
| RCC_CFGR_PPRE2_DIV1
| RCC_CFGR_PPRE1_DIV2
| RCC_CFGR_HPRE_DIV1
| RCC_CFGR_SW_HSI;
RCC->CR = _VAL2FLD(RCC_CR_HSITRIM,16) | RCC_CR_PLLON | RCC_CR_HSEON | RCC_CR_HSION;
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR = RCC_CFGR_MCO_PLL
| RCC_CFGR_I2SSRC_SYSCLK
| RCC_CFGR_USBPRE_DIV1_5
| RCC_CFGR_PLLMUL9
| RCC_CFGR_PLLSRC_HSE_PREDIV
| RCC_CFGR_PPRE2_DIV1
| RCC_CFGR_PPRE1_DIV2
| RCC_CFGR_HPRE_DIV1
| RCC_CFGR_SW_PLL;
Вс фев 13, 2022 22:54:17
Вс фев 13, 2022 23:04:13
ConfigList<PinMode::PushPull_LowSpeed<1>, PA_15, // Подтяжка
PinMode::AF_PushPull_HighSpeed<14>, PA_11, PA_12, // PA11=USBDM, PA12=USBDP
PinMode::AF_PushPull_HighSpeed_PullUp<0x0>, PA_13, // PA13=SWDIO
PinMode::AF_PushPull_LowSpeed_PullDown<0x0>, PA_14, // PA14=SWCLK
PinMode::Input_Floating, CfgCmd::AllUnusedPins
>::pwr_config();
Вс фев 13, 2022 23:20:27
Вс фев 13, 2022 23:25:59
Вс фев 13, 2022 23:43:11
Вс фев 13, 2022 23:45:33
Пн фев 14, 2022 09:19:04
addr = 1000DB44; SP = 1000CF98; m = 1000CFA0
1: y1 = 1.000000; y2 = 2.000000
2: y1 = 1.000000; y2 = 2.000000
void Zf2()
{
uint32_t m[8];
memset(m, 0xEE, sizeof(m));
__set_MSP(__get_MSP() + 4);
printf("y1 = %f; y2 = %f", 1.0f, 2.0f);
__set_MSP(__get_MSP() - 4);
}
Пн фев 14, 2022 12:10:03
Пн фев 14, 2022 12:16:06
TRUE_INLINE void StartHSI(){ // system bus 48MHz from PLL
__IO uint32_t StartUpCounter = 0;
#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}}while(0)
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSION;
// To adjust HSI set value of HSITRIM here
WAITWHILE(!(RCC->CR & RCC_CR_HSIRDY));
FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) |
FLASH_ACR_LATENCY_0 | FLASH_ACR_PRFTBE;
RCC->CFGR = RCC_CFGR_PLLSRC_HSI_DIV2 | RCC_CFGR_PLLMUL12 | RCC_CFGR_USBPRE_DIV1 | RCC_CFGR_PPRE1_DIV2;
RCC->CR |= RCC_CR_PLLON; // Enable PLL
// Wait till PLL is ready
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
// Select PLL as system clock source
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// Wait till PLL is used as system clock source
WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
#undef WAITWHILE
}
// @return 1 if OK, 0 if failed
TRUE_INLINE int StartHSE(){ // system bus 72MHz from PLL
__IO uint32_t StartUpCounter = 0;
#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}; if(x) return 0;}while(0)
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSEON; // disable PLL to reconfigure, enable HSE
WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
// Enable Prefetch Buffer. Flash 4 wait states for 48..72MHz
FLASH->ACR = (FLASH->ACR & ~(FLASH_ACR_LATENCY)) |
FLASH_ACR_LATENCY_2 | FLASH_ACR_PRFTBE;
// HCLK = SYSCLK (AHB prescaler = 1), PCLK1 = HCLK/2 (APB1 prescaler = 2, max freq = 36MHz),
// PCLK2 = HCLK (APB2 prescaler = 1), PLLCLK = HSE * 9 = 72MHz
RCC->CFGR = RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL9 | RCC_CFGR_PPRE1_DIV2;
RCC->CR |= RCC_CR_PLLON; // Enable PLL
// Wait till PLL is ready
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
// Select PLL as system clock source
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// Wait till PLL is used as system clock source
WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
#undef WAITWHILE
return 1;
}
Пн фев 14, 2022 12:51:06
The ARMv7-M architecture guarantees that stack pointer values are at least 4-byte aligned. However, some software standards require the stack pointer to be 8-byte aligned, and the architecture can enforce this alignment.
void Zf2(double* p)
{
uint32_t m[32];
memset(m, 0xEE, sizeof(m));
__set_MSP(__get_MSP() + 4);
rtt.println<"y1 = {}; y2 = {}">(p[0], p[1]); // y1 = 1; y2 = 2
__set_MSP(__get_MSP() - 4);
}
Пн фев 14, 2022 13:02:04
0xED94 0x0B02 VLDR D0,[R4, #+8]
0xED8D 0x0B00 VSTR D0,[SP, #+0]
Пн фев 14, 2022 13:11:29
Пн фев 14, 2022 13:18:45
Пн фев 14, 2022 13:23:25
// USBPRE bit must be valid before enabling the USB clock!
Пн фев 14, 2022 13:28:24
GPIOA->MODER = (GPIOA->MODER & (~GPIO_MODER_MODER15_Msk | GPIO_MODER_MODER11_Msk | GPIO_MODER_MODER12_Msk)) |
GPIO_MODER_MODER11_AF | GPIO_MODER_MODER12_AF | GPIO_MODER_MODER15_O;
// USB - alternate function 14
GPIOA->AFR[1] = (GPIOA->AFR[1] & ~(GPIO_AFRH_AFRH4_Msk | GPIO_AFRH_AFRH5_Msk)) |
(14 << (4 * 4)) | (14 << (5 * 4));
(14 << (3 * 4)) | (14 << (4 * 4));
Пн фев 14, 2022 14:39:35
Пн фев 14, 2022 18:06:24
Каким образом он у тебя включенным оказался?
С этим надо что-то делать любым доступным тебе способом.
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER15_Msk | GPIO_MODER_MODER11_Msk | GPIO_MODER_MODER12_Msk))
800119c: f022 4243 bic.w r2, r2, #3271557120 ; 0xc3000000
80011a0: f422 0240 bic.w r2, r2, #12582912 ; 0xc00000