Ср июл 05, 2023 12:31:46
master_arr [countSPIb] = SPDR1; // получаем байт от мастера
SPDR = master_arr [countSPIb]; // отдаем байт обратно
countSPIb++; // увеличиваем счетчик
//SPDR = slave_arr [countSPIb]; // отдаем байт ведомого (+1 индекс)
PORTC |= (1<<1);
Ср июл 05, 2023 12:52:51
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24);
Ср июл 05, 2023 12:53:07
Это я для краткости так написал, видимо не хватает разрядности fG. Если так, то в результате fG всегда = 0 будет. Переделайте эту строку на ваш предыдущий код с темповой переменной.warptred12 писал(а):Так же ругается на эту строчку:
Ср июл 05, 2023 13:43:06
// Массив корторый приходит от мастера
volatile unsigned long int master_arr [4];
// Массив который отдаем от мастеру
volatile unsigned long int slave_arr [4];
#include <mega8.h>
#include <math.h>
#include <io.h>
#include <delay.h>
#define F_CPU (8000000)
#define VFG_TIMER_MAX (65535)
#define VFG_DDR DDRD
#define VFG_PORT PORTD
volatile unsigned long int fG;
unsigned char nG;
unsigned int N[]={1,8,64,256,1024};
// Массив корторый приходит от мастера
volatile unsigned long int master_arr [4];
// Массив который отдаем от мастеру
volatile unsigned long int slave_arr [4];
// счетчик входящих байт
volatile int countSPIb = -1;
volatile char reqID = 0;
void setup (void)
{
#asm("cli")
// Настройка SPI как SLAVE
DDRB |= (1 << PORTB4); // Настроить вывод MISO на выход
SPCR |= (1 << SPIE) | (1 << SPE) | (0 << MSTR); // Прерывание включено и сам SPI как SLAVE
#asm("sei")
}
interrupt [SPI_STC] void spi_isr(void) // Прерывание SPI1 - пришел байт
{
switch(reqID) {
case 0:
master_arr[0] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 1:
master_arr[1] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 2:
master_arr[2] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 3:
master_arr[3] = SPDR;
SPDR = master_arr [reqID];
reqID = 0;
countSPIb = -1;
break;
}
}
//***********************************************timer1************************************************
void Tim1Init(void)
{
#asm("cli")
TCCR1A = (1<<COM1A0); //toggle on compare
TCCR1B = (1<<WGM12)|(1<<CS12)|(1<<CS10); // set timer CTC mode, prescaler 1024
TIMSK = (1<<OCIE1A);
#asm("sei")
}
void SetUpTim1A(unsigned long int Foc) //calculate value OCR1A register
{
unsigned long int TimDiv;
unsigned char ClockSelect=0;
unsigned char i=0;
for(i=0;i<=4;i++) {
TimDiv = 1*((F_CPU/(Foc*N[i])-1));
if(TimDiv >= 0 && TimDiv<VFG_TIMER_MAX){
ClockSelect=i+1;
break;
}
}
#asm("cli")
OCR1A=TimDiv;
TCCR1B = (1<<WGM12) | (ClockSelect<<CS10);
#asm("sei")
}
void UpdateTim1A(unsigned long int freq) //old value storage
{
static unsigned long int fG_old = 0;
if (fG_old != freq)
{
SetUpTim1A(freq);
fG_old = freq;
}
}
interrupt [TIM1_COMPA] void timer1_compa_isr(void)
{
VFG_PORT = (VFG_PORT^nG)&(nG);
}
void main(void)
{
static unsigned long int fG_old = 0;
VFG_DDR = 0b00000111;
DDRC = 0b11111111;
setup();
Tim1Init();
#asm
in r30,spsr
in r30,spdr
#endasm
#asm("sei")
for(;;) {
if(PINB.2==0) {countSPIb = -1;} //сброс в случае глюка связи
if (fG_old != fG) { //old value detction
SetUpTim1A(fG);
fG_old = fG;
}
if (countSPIb >= sizeof(master_arr)){
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24);
UpdateTim1A(fG);
SetUpTim1A(fG);
countSPIb = -1;
}
}
}
Чт июл 06, 2023 01:08:48
interrupt [SPI_STC] void spi_isr(void) // Прерывание SPI1 - пришел байт
{
switch(reqID) {
case 0:
master_arr[0] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 1:
master_arr[1] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 2:
master_arr[2] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
case 3:
master_arr[3] = SPDR;
SPDR = master_arr [reqID];
reqID++;
//reqID = 0;
//countSPIb = -1;
break;
}
}
...
...
void main(void)
{
...
for(;;) {
...
if (reqID>= sizeof(master_arr)){
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24);
UpdateTim1A(fG);
SetUpTim1A(fG);
reqID= 0;
}
}
}
Чт июл 06, 2023 11:43:39
#include <mega8.h>
#include <math.h>
#include <io.h>
#include <delay.h>
#define F_CPU (8000000)
#define VFG_TIMER_MAX (65535)
#define VFG_DDR DDRD
#define VFG_PORT PORTD
volatile unsigned long int fG;
unsigned char nG;
unsigned int N[]={1,8,64,256,1024};
//BYTE STORAGE
volatile unsigned long int master_arr [4];
//BYTE COUNTER
volatile int reqID = 0;
void setup (void)
{
#asm("cli")
DDRB |= (1 << PORTB4); //configure MISO as output
SPCR |= (1 << SPIE) | (1 << SPE) | (0 << MSTR); //configure slave mod and interrupt
#asm("sei")
}
interrupt [SPI_STC] void spi_isr(void)
{
switch(reqID) {
case 0:
master_arr[0] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<0);
reqID++;
break;
case 1:
master_arr[1] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<1);
reqID++;
break;
case 2:
master_arr[2] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<2);
reqID++;
break;
case 3:
master_arr[3] = SPDR;
SPDR = master_arr [reqID];
reqID++;
break;
}
}
//***********************************************timer1************************************************
void Tim1Init(void)
{
#asm("cli")
TCCR1A = (1<<COM1A0); //toggle on compare
TCCR1B = (1<<WGM12)|(1<<CS12)|(1<<CS10); // set timer CTC mode, prescaler 1024
TIMSK = (1<<OCIE1A);
#asm("sei")
}
void SetUpTim1A(unsigned long int Foc) //calculate value OCR1A register
{
unsigned long int TimDiv;
unsigned char ClockSelect=0;
unsigned char i=0;
for(i=0;i<=4;i++) {
TimDiv = 1*((F_CPU/(Foc*N[i])-1));
if(TimDiv >= 0 && TimDiv<VFG_TIMER_MAX){
ClockSelect=i+1;
break;
}
}
#asm("cli")
OCR1A=TimDiv;
TCCR1B = (1<<WGM12) | (ClockSelect<<CS10);
#asm("sei")
}
void UpdateTim1A(unsigned long int freq) //old value storage
{
static unsigned long int fG_old = 0;
if (fG_old != freq)
{
SetUpTim1A(freq);
fG_old = freq;
}
}
interrupt [TIM1_COMPA] void timer1_compa_isr(void)
{
VFG_PORT = (VFG_PORT^nG)&(nG);
}
void main(void)
{
static unsigned long int fG_old = 0;
VFG_DDR = 0b00000111;
DDRC = 0b11111111;
setup();
Tim1Init();
#asm("sei")
for(;;) {
if (fG_old != fG) { //old value detction
SetUpTim1A(fG);
fG_old = fG;
}
if (reqID>= sizeof(master_arr)){
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24); //generator freqency
UpdateTim1A(fG);
SetUpTim1A(fG);
reqID= 0;
}
}
}
Чт июл 06, 2023 13:26:54
if (reqID>= sizeof(master_arr)){
PORTC |= (1<<0);
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24); //generator freqency
UpdateTim1A(fG);
SetUpTim1A(fG);
reqID= 0;
_delay_ms(500);
PORTC &= ~(1<<0);
}
Чт июл 06, 2023 13:28:42
Чт июл 06, 2023 14:26:06
Чт июл 06, 2023 14:44:08
Чт июл 06, 2023 14:56:25
if (reqID >= sizeof(arr) / sizeof(arr[0])) ...
Чт июл 06, 2023 15:05:11
if (reqID >= (sizeof(arr) / sizeof(arr[0]))) ...
Чт июл 06, 2023 15:10:10
for(;;) {
if (fG_old != fG) { //old value detction
SetUpTim1A(fG);
fG_old = fG;
}
PORTC &= ~(1<<0);
PORTC &= ~(1<<1);
PORTC &= ~(1<<2);
PORTC &= ~(1<<3);
if (reqID >= (sizeof(arr) / sizeof(arr[0]))){
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24); //generator freqency
UpdateTim1A(fG);
SetUpTim1A(fG);
delay_ms(1);
PORTC &= ~(1<<4);
reqID= 0;
}
}
Чт июл 06, 2023 15:11:03
C Operator Precedence:
...
3 : /
...
6 : >=
...
Чт июл 06, 2023 15:19:49
Чт июл 06, 2023 15:24:16
Чт июл 06, 2023 15:31:05
Чт июл 06, 2023 15:31:53
Чт июл 06, 2023 15:44:10
#include <mega8.h>
#include <math.h>
#include <io.h>
#include <delay.h>
#define F_CPU (8000000)
#define VFG_TIMER_MAX (65535)
#define VFG_DDR DDRD
#define VFG_PORT PORTD
volatile unsigned long int fG;
unsigned char nG;
unsigned int N[]={1,8,64,256,1024};
//BYTE STORAGE
volatile unsigned long int master_arr [4];
//BYTE COUNTER
volatile int reqID = 0;
void setup (void)
{
#asm("cli")
DDRB |= (1 << PORTB4); //configure MISO as output
SPCR |= (1 << SPIE) | (1 << SPE) | (0 << MSTR); //configure slave mod and interrupt
#asm
in r30,spsr
in r30,spdr
#endasm
#asm("sei")
}
interrupt [SPI_STC] void spi_isr(void)
{
switch(reqID) {
case 0:
master_arr[0] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<0);
reqID++;
break;
case 1:
master_arr[1] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<1);
reqID++;
break;
case 2:
master_arr[2] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<2);
reqID++;
break;
case 3:
master_arr[3] = SPDR;
SPDR = master_arr [reqID];
PORTC |= (1<<3);
reqID++;
break;
}
}
//***********************************************timer1************************************************
void Tim1Init(void)
{
#asm("cli")
TCCR1A = (1<<COM1A0); //toggle on compare
TCCR1B = (1<<WGM12)|(1<<CS12)|(1<<CS10); // set timer CTC mode, prescaler 1024
TIMSK = (1<<OCIE1A);
#asm("sei")
}
void SetUpTim1A(unsigned long int Foc) //calculate value OCR1A register
{
unsigned long int TimDiv;
unsigned char ClockSelect=0;
unsigned char i=0;
for(i=0;i<=4;i++) {
TimDiv = 1*((F_CPU/(Foc*N[i])-1));
if(TimDiv >= 0 && TimDiv<VFG_TIMER_MAX){
ClockSelect=i+1;
break;
}
}
#asm("cli")
OCR1A=TimDiv;
TCCR1B = (1<<WGM12) | (ClockSelect<<CS10);
#asm("sei")
}
void UpdateTim1A(unsigned long int freq) //old value storage
{
static unsigned long int fG_old = 0;
if (fG_old != freq)
{
SetUpTim1A(freq);
fG_old = freq;
}
}
interrupt [TIM1_COMPA] void timer1_compa_isr(void)
{
VFG_PORT = (VFG_PORT^nG)&(nG);
}
void main(void)
{
static unsigned long int fG_old = 0;
VFG_DDR = 0b00000111;
DDRC = 0b11111111;
setup();
Tim1Init();
#asm
in r30,spsr
in r30,spdr
#endasm
#asm("sei")
for(;;) {
if (fG_old != fG) { //old value detction
SetUpTim1A(fG);
fG_old = fG;
}
PORTC &= ~(1<<0);
PORTC &= ~(1<<1);
PORTC &= ~(1<<2);
PORTC &= ~(1<<3);
if (reqID >= (sizeof(master_arr) / sizeof(master_arr[0])/ sizeof(master_arr[1])/ sizeof(master_arr[2])/ sizeof(master_arr[3])))
{
nG = master_arr[0]; //generator number
fG = (master_arr[1] << 8)|(master_arr[2] << 16)|(master_arr[3] << 24); //generator freqency
UpdateTim1A(fG);
SetUpTim1A(fG);
delay_ms(1);
PORTC &= ~(1<<4);
reqID= 0;
}
}
}
Чт июл 06, 2023 15:47:52
if (reqID >= (sizeof(master_arr) / sizeof(master_arr[0])/ sizeof(master_arr[1])/ sizeof(master_arr[2])/ sizeof(master_arr[3]))